Electronic circuits are typically constructed in the form of a printed circuit board (PCB) that includes a plurality of electronic components soldered to a circuit board substrate having conductive traces interconnecting various device terminals to form an electrical circuit. As PCBs and the implemented electrical circuits thereof are often complex, board testing at manufacture has become increasingly automated. In this respect, board testing apparatus has evolved from simple I/O functional testers that connect to I/O connectors of a populated PCB for high level automated functional testing, to so-called “bed of nails” test fixtures that include probe pins to make electrical contact with all or some circuit nodes of a tested board for performance of high level and some lower level testing, to integrated testing devices that provide for automated testing of a PCB without the need to externally probe individual circuit nodes. The Joint Test Action Group (JTAG) has developed a circuit board testing standard IEEE 1149.1 including Test Access Port (TAP) and boundary scan testing of hardware via test devices included on the tested boards. The boundary scan type testing involves controlling and monitoring boundary pins of a JTAG compatible device under control of software to provide test coverage beyond that which might be possible using ordinary bed of nails fixturing. This is particularly true of modern multi-layer boards with dense coverage of the top and bottom by fine-pitch components where there is often no external access to many circuit nodes routed through internal layers and underneath component parts, where boundary scan techniques have become widely accepted in industry.
The JTAG devices are connected via a serial data link providing commands to the devices so as to allow controlled temporary isolation of the pins of JTAG compatible devices. In this arrangement, the pin on one isolated JTAG device can be set to a known test state voltage and the voltage of a pin on another isolated JTAG compatible device can be measured to determine whether the monitored pin is in the correct state. Thus, the boundary scan technique can be employed in conjunction with a series of predetermined test vectors to test any number of circuit nodes on a PCB in automated fashion. The output tested node states can then be compared with the correct states to ascertain any circuit board failures, whether in the board itself or in one or more components soldered to a populated board.
Many modern circuit boards include processor systems, whether microprocessors, microcontrollers, programmable logic, DSPs, etc., and associated circuitry (processor, system controller, etc.). Testing of such processor-based PCBs using the IEEE 1149.1 TAP boundary scan techniques has heretofore been performed under control of the on-board processor to provide controlled boundary scan as a diagnostic feature upon powering up the board. In these implementations, the processor and associated components on the board must be functional to read test vectors from memory and to either shift the vectors out through a serial port or pass them to a hardware device that shifts them to the TAP system on the board. In this configuration, however, boundary scan testing is not possible if there are problems in the processor, memory, or other associated circuitry, as the testing is reliant upon the processor to manage the boundary scan devices. Furthermore, even if the processor-related circuitry is functional to allow the boundary scan tests to run, this testing cannot include the processor-related circuitry itself, whereby on-board processor controlled boundary scan testing provides less than complete test coverage. In a manufacturing setting, external boundary scan test controls can be connected to a PCB to implement testing of the processor and related circuits, with the processor being held in a reset state during testing. While this form of external boundary scan test control provides a higher level of test coverage, this feature does not aid in field diagnostic testing where PCBs must often be verified in a field installation with no access by external test equipment. Thus, there remains a need for improved boundary scan testing apparatus and methodologies by which better test coverage can be obtained for printed circuit boards without the need for external boundary scan test controllers.